A Reconfigurable Hardware Implementation of the One-Dimensional Discrete Wavelet Transform

—ASIC hardware implementations of the discrete wavelet transform are required to cope with the intensive real-time computations of the transform. In this paper, we describe a parallel implementation of the wavelet transform using one type of reconfigurable ASICs; Filed Programmable Gate Arrays (FPGAs). The implementation is based on reformulating the transform using the distributed arithmetic and ployphase decomposition techniques, so that the ample inherent parallelism of the transform can be well exploited by the fine-grained parallel architecture of Virtex FPGAs. Performance results demonstrate the applicability of FPGAs with distributed arithmetic and polyphase decomposition to achieve the required high computational speeds of the discrete wavelet transform.